1. Field of the Invention
The present invention relates to a liquid crystal display device and a method of driving an LCD panel, more particularly to an LCD panel drive technique for achieving both of time-division drive and inversion drive.
2. Description of the Related Art
The time-division drive, in which a set of data lines (signal lines) are sequentially selected and data signals are time-divisionally written into desired pixels, is one of the commonly-used techniques in driving the LCD panel (See Japanese Laid-Open Patent Application No. JP-A Heisei 11-327518, and JP-A 2003-215540, for example). One advantage of the time-division drive is that the time-division drive effectively reduces the number of output amplifiers integrated within the LCD driver. A liquid crystal display device using the time-division drive can achieve driving pixels with a fewer number of output amplifiers than the number of data lines of the liquid crystal display panel. This effectively reduces the power consumption and chip size of the LCD driver. Another advantage is that the time-division drive effectively reduces the number of connection lines between the LCD driver and the LCD panel through incorporating a switch circuitry within the LCD panel for selecting data lines. The switch circuitry incorporated within the LCD panel effectively reduces the number of connection lines that provides electrical connections between the LCD driver and the LCD panel below the number of data lines within the LCD panel. The reduction in the number of connection lines between the LCD driver and the LCD panel effectively facilitates the installation of the LCD driver and the LCD panel, and effectively reduces the EMI (electromagnetic interference). The recent increase in the number of the pixels integrated within the LCD panel necessitates an increase in the number of data lines that are time-divisionally driven.
The inversion drive is another commonly-used technique for driving the LCD panel. The inversion drive is a technique in which the polarities of data signals are inverted at predetermined spatial and time cycles for avoiding the “burn-in” phenomenon. The inversion drive reduces DC components of drive voltages fed to respective pixels, and thereby effectively avoids the “burn-in” phenomenon.
Generally speaking, there are two kinds of inversion drive: the common constant drive and the common inversion drive. The common constant drive technique designates a technique in which the data signals are inverted with the voltage level of the common electrode (or the backplane electrode) kept constant at a certain voltage level, which is referred to as the common level VCOM, hereinafter. The common inversion drive technique designates a technique in which both of the voltage levels of the data signals and the common electrode are inverted. The common constant drive technique advantageously stabilizes the voltage level of the common electrode compared to the common inversion drive technique, and this leads to significant reduction in the flicker of the image on the LCD panel, as known in the art. As described in the following, the present invention is directed to the common constant drive technique.
The dot inversion drive, which is one sort of the common inversion drive technique, is a technique in which data signals with opposite polarities are written into adjacent pixels. It should be noted that the polarity of a data signal is defined with respect to the common voltage level VCOM (that is, the voltage level of the common electrode). When a data signal has a signal level higher than the common voltage level VCOM, the polarity of the data signal is defined as being “positive”. When a data signal has a signal level lower than the common voltage level VCOM, on the other hand, the polarity of the data signal is defined as being “negative”. Advantageously, the dot inversion drive further improves the stability in the voltage level of the common electrode by feeding positive and negative data signals to the LCD panel at the same time, and thereby effectively reduces the flicker on the LCD panel.
FIG. 1A is a circuit diagram illustrating a typical structure of a liquid crystal display device adopting both of the time-division drive and the dot inversion drive, which is denoted by the numeral 100. It should be noted that a liquid crystal display device adopting both of the time-division drive and the dot inversion drive is disclosed in the above-mentioned Japanese Laid-Open Patent Application No. JP-A Heisei 11-327518, for example. The liquid crystal display device 100 is provided with an LCD panel 101 and an LCD driver 102. The LCD panel 101 is provided with gate lines (scan lines) 111, data lines (signal lines) 112, and pixels 113 arranged in rows and columns. The gate lines 111 are used to select the rows of the pixels 113. Although only a portion of the LCD panel 101 is illustrated in FIG. 1A, it is understood that the LCD panel 101 further includes gate lines 111, data lines 112, and pixels 113 which are not shown. The pixels 113 connected to the gate line 111i may be referred to as the pixels 113 in the i-th line. As shown in FIG. 1B, the pixels 113 are each provided with a TFT 114, and a pixel electrode 115. The pixel electrodes 115 are opposed to the common electrode (backplane electrode) 116, and liquid crystal capacitors are formed between the respective pixel electrodes 115 and the common electrode 116. Although the common electrode 116 is illustrated as being separately provided in each pixel 113 in FIG. 1B, it is understood that the common electrode 116 is a single large electrode, as well known in the art.
Referring back to FIG. 1A, the LCD panel 101 additionally includes one input node 117 for three data lines 112. Hereinafter, the input nodes 117 positioned in the odd-numbered position may be referred to as the odd input nodes 117O, and the input nodes 117 positioned in the even-numbered position may be referred to as the even input nodes 117E.
It should be noted that a set of data lines 112 connected to a certain input node 117 (through switch elements) may be referred to as the data lines 112 “associated with” the certain input node 117. In the liquid crystal display device 100 shown in FIG. 1A, three data lines associated with the same input node 117 are time-divisionally driven.
Correspondingly, pixels 113 connected to a certain input node 117 (through data lines 112) may be referred to as the pixels 113 “associated with” the certain input node 117. In FIG. 1A, the pixels 113 which are connected with the same gate line 111 and associated with the same input node 117 are time-divisionally driven.
Referring back to FIG. 1A, the pixels 113 includes pixels used to display the red color (referred to as R pixels, hereinafter), pixels used to display the green color (referred to as G pixels, hereinafter), and pixels used to display the blue color (referred to as B pixels, hereinafter). Hereinafter, R pixels associated with the odd input node 117O may be referred as the R pixels 113R1, and R pixels associated with the even input node 117E may be referred as the R pixels 113R2. Correspondingly, G pixels associated with the odd input node 117O may be referred as the G pixels 113G1, and G pixels associated with the even input node 117E may be referred as the G pixels 113G2. Furthermore, B pixels associated with the odd input node 117O may be referred as the B pixels 113B1, and B pixels associated with the even input node 117E may be referred as the B pixels 113B2.
The pixels 113 connected to the same data line 112 are associated with the same color. Hereinafter, the data lines connected to the R pixels 113R1 and 113R2 may be referred to as the data lines 112R1 and 112R2, respectively. Correspondingly, the data lines connected to the G pixels 113G1 and 113G2 may be referred to as the data lines 112G1 and 112G2, respectively, and the data lines connected to the B pixels 113B1 and 113B2 may be referred to as the data lines 112B1 and 112B2, respectively.
The data lines 112R1, 112G1, and 112B1 are connected to the associated odd input nodes 117O through switches 119R1, 119G1, and 119B1, respectively, and the data lines 112R2, 112G2; and 112B2 are connected to the associated even input nodes 117E through switches 119R2, 119G2, and 119B2. The switches 119R1, 119G1, 119B1, 119R2, 119G2, and 119B2 are turned on and off in response to control signals RSW, GSW, and BSW. The selection of desired data lines is achieved by turn-on of desired ones of the switches 119R1, 119G1, 119B1, 119R2, 119G2, and 119B2.
The input nodes 117 of the LCD panel 101 are connected to output terminals of the LCD driver 102, respectively. The output terminals of the LCD driver 102 may be denoted by the symbols “Source1”, “Source2” . . . , respectively.
The LCD driver 102 feeds data signals having desired signal levels to selected pixels, that is, the pixels 113 connected to selected data lines 112 and a selected gate line 111. The pixels 113 are set to the grayscale levels associated with the signal levels of the data signals fed thereto.
It is necessary to determine the polarities of the data signals developed on the respective output terminals of the LCD driver 102 so as to be adapted to the dot inversion drive and the time-division drive. In the dot inversion drive, as shown in FIG. 2, two pixels 113 adjacent in the horizontal or vertical direction are fed with data signals with opposite polarities. It should be noted that the horizontal direction is the direction in which the gate lines (scan lines) are extended, and the vertical direction is the direction in which the data lines (signal lines) are extended. It should be also noted that the symbols “R1”, “G1”, “B1”, “R2”, “G2”, and “B2” indicate the R pixels 113R1, G pixels 113G1, B pixels 113B1, R pixels 113R2, G pixels 113G2, and B pixels 113B2, respectively.
With respect to the pixels 112 in the first line, as shown in FIG. 1A, the R pixels 113R1, B pixels 113B1, and G pixels 113G2 are fed with data signals with the positive polarity, and the G pixels 113G1, R pixels 113R2, and B pixels 113B2 are fed with data signals with the negative polarity. In FIG. 1A, the polarities of the respective data signals fed to the pixels 113 in the first line are indicated by the signals “+” and “−” superposed on the data lines 112.
On the other hand, three data lines 112 associated with the same input node 117 are sequentially selected in each horizontal period from end to end. In other words, as shown in FIG. 3, the pixels 113 connected to the same gate lines are driven in this order of R pixels, G pixels, and B pixels. As shown in FIG. 4, driving the pixels 113 in such order can be achieved by activating the control signals RSW, GSW, and BSW in this order.
From the viewpoint of the drive sequence of the pixels 113 and the polarities of the data signals fed thereto, it is necessary that the polarities of the respective data signals sequentially outputted from the output terminals Source1 and Source2 of the LCD driver 102 are set as shown in FIG. 5. Specifically, in the first horizontal period (that is the period for driving the pixels 113 in the first line), a data signal of the positive polarity, a data signal of the negative polarity, and another data signal of the positive polarity are sequentially outputted from the output terminal Source1, while a data signal of the negative polarity, a data signal of the positive polarity, and another data signal of the negative polarity are sequentially outputted from the output terminal Source2. In the second horizontal period, on the other hand, a data signal of the negative polarity, a data signal of the positive polarity, and another data signal of the negative polarity are sequentially outputted from the output terminal Source1, while a data signal of the positive polarity, a data signal of the negative polarity, and another data signal of the positive polarity are sequentially outputted from the output terminal Source2.
It should be noted that the data signals developed on the output terminals Source1 and Source 2 of the LCD driver 102 are always opposite, that is, data signals of the positive and negative polarities are always written into the selected pixels at the same time. This is important for reducing the change in the voltage level of the common electrode.
One issue is that such liquid crystal display device requires frequently inverting the voltage levels on the nodes along the paths used to distribute data signals to the respective data lines (such as, the output terminals of the LCD driver 102). For example, the operation shown in FIG. 5 requires inverting the polarities of the data signals developed on the output terminals of the LCD driver 102 three times per one horizontal period. Frequent inversion of the data signals undesirably causes a significant increase in the power consumption of the LCD driver 102, since the output terminals of the LCD driver 102 has a considerable load capacitance.
Japanese Laid-Open Patent Application No. JP-A 2003-215540, on the other hand, discloses a technique adapted to the time-division drive, in which the frequency of the inversion of the data signals outputted from an LCD driver is reduced down to once per two horizontal periods. In this technique, however, the spatial frequency of the inversion of the data signals fed to the respective pixels 112 are two pixels. In other words, this technique does not provide the dot inversion drive.
As thus described, the conventional liquid crystal display devices suffer from a problem that the use of both of the time-division drive and the dot inversion drive is inevitably accompanied by the frequent inversion of the voltage levels on the nodes along the paths used to distribute data signals to the respective data lines, causing the increase in the power consumption of the LCD driver.